The present invention relates to clock generation circuits for integrated circuit devices, and more particularly, to delay locked loop (DLL) circuits.
As the processing speed of electronic systems has increased, there has been increased focus on high-speed inter-chip signaling. High-speed inter-chip communication often requires precise clock signals for clocking data signals, and is often desirable that such clock signals provide such precision over a wide range of clock frequencies. Phase-locked loop (PLL) or DLL circuits are commonly used to produce such precision clock signals.
Some conventional DLL circuits use phase interpolators to provide fine phase adjustment of clock signals. For example, in some conventional approaches, a first DLL loop is used to create a plurality of quadrature clock signals. A selected pair of these quadrature clock signals is then applied to a phase interpolator loop, which generates a clock with a phase that is interpolated between the selected quadrature clocks. An exemplary dual-loop DLL circuit along these lines is described in an article by Sidiropolous and Horowitz et al. entitled “A Semi-Digital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 32, no. 11 (November 1997). Other dual loop circuits are described in “Pixel-Flow System Documentation: IV.9 Clock Input Buffer and Delay-Locked Loop,” University of North Carolina, rev. 6.0 (Jan. 23, 2001), available on the World Wide Web at www.cs.unc.edu/˜msl/PadLibrary/IV.9.pdf.
Although these and other prior art DLL circuits can provide precision clock control, there is an ongoing need for DLL circuits that can provide precision phase control and wide operating range.